Signal Integrity analysis
Do you need help for the Signal Integrity (SI) of your design? Sintecs is your partner for Signal Integrity analysis services. We provide a complete SI analyis of your board including standard SI, crossstalk and multi-gigabit signalling. Contact us your your Signal Integrity analysis need. We can supply you with a referce SI analysis report to demonstrate our analysis capabilities.
Racing against the clock and faced with the increasing rise/fall time of logic (e.g. for DDR2, DDR3 and DDR4 designs), most of today's high-speed designers must be concerned with the signal integrity of their designs. Sintecs provides signal integrity analysis services to help you address these issues.
In the past, many companies completed their high-speed designs by employing a high-speed expert to advise the layout designer on the routing of critical signals. If applied at all, signal integrity analysis tools were run against the resulting layout and any problems were solved interactively. This was a satisfactory, but expertise-intensive approach for many companies.
As interface speeds exceed 1GHz and edge rates drop below 100ps, new methods must be adopted. In such high-end designs, interfaces can connect several CPUs and span several boards. High-speed behavior is no longer limited to a few critical signals and can often affect more than 80% of the signals on the board. Each major net/bus must be considered as an entity and a strategy developed for implementing the signals for each net/bus.
Transmission line behavior has become so complex that simulation is essential to augment designer experience. Manufacturing tolerances (e.g. slow/fast devices or the allowable range of characteristic impedance) must be taken into account to ensure that the resulting design can function within specifications under all possible worst-case conditions.
Traditional post-layout analysis is no longer enough to guarantee design success. Designers must be able to evaluate alternative layout strategies before layout begins, taking into account allowable manufacturing tolerances. As a strategy for each net/bus is developed, rules are defined for a layout that ensures that the net/bus will work under real world conditions.
By using high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.
For more information about our signal integrity analysis services and other services we provide, feel free to contact us for a free quote.