In modern system design, electronic devices rely on stable DDR (double data rate) memory for fast, reliable operation. Time spend for product testing is limited due to a shortened time to market, but when microprocessor-based products are released with unstable memory, this can lead to a costly recall.
A shortened time to market, often limits the amount of product testing that can be performed. Microprocessor-based products released with unstable memory may experience only intermittent failures, but even those can lead to a costly recall. To minimize that risk, comprehensive memory timing analysis need to be performed during the design phase of the product.
Timing analysis/verification becomes challenging as complex designs include multifunctional devices with aggressive multiple timing variations.
Net topologies, trace impedances and terminations play an important role in waveform integrity. Trace length, vias and cross talk play an important role in timing.
A combined signal integrity analysis and timing analysis environment is needed to guarantee proper function of the DDR interface.
In most cases, the DRAM timing models are quite standard, since JEDEC specifies the timing requirements at the DRAMs. For the Controllers, the requirements can vary from manufacturer to manufacturer and chip to chip. Default Controller timing models are often used as a starting point to do timing analysis but creation of component specific timing model is needed if the parameters of your Controller differ quite a bit from the default Controller timing model. To create component specific timing models, it is needed to understand the required parameters from the datasheet, understand how they are defined, and interpret them to create a specific model.
JEDEC timing requirements
In the JESD79 and JESD208 documents, more information can be found about the different DDRx specification.
Thorough knowledge of the different timing parameters within a DDRx device is mandatory for performing detailed accurate timing analysis.
By using high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.