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EMC verification

EMC verification

Racing against the clock and faced with the increasing rise time of logic, most of today's high-speed designers are concerned with the radiation of their design. Sintecs can help you address the EMC issues of your design. Sintecs provides on-site EMC analysis methodology training as well as on-site EMC analysis support.

Most designers are aware that multilayer boards provide better EMC control than double-sided boards, and that embedding traces between planes can suppress EMC dramatically. However, people still make double-sided boards and route high speed traces on surface layers due to the overriding factor of "cost".
In reality, of course, "cost" is not only the monetary expense of the board. There is also the cost of violating design rules for timing, manufacturing, thermal and other product concerns.

EMC verification

The real challenge thus facing designers is to achieve a good EMC design in a "cost-effective" day. However, knowing the "cost" is only half the story. To assess the "effectiveness" of implementing specific EMC rules or EMC fixes, early stage simulations are required to quantify EMC problems. The ability of EMC simulations to quantify EMC problems not only allows early identification of critical areas but also assessment of the effectiveness of various EMC reduction solutions.

All time varying currents in a system, whether intended or undesired, radiate. In order to understand EMC better, it is essential to think in terms of currents rather than voltages and in terms of the frequency domain rather than the time domain. It is also important to bear in mind that currents radiate more efficiently at higher rather than lower frequencies. Noise currents induced on cables or shields, though much smaller than intended signal currents, can also radiate more significantly (this is because the cables or shields to which they are attached make good antennas).

In a typical system, many EMC mechanisms are impossible to track completely. In fact, some mechanisms are still not properly understood. Fortunately, it is not necessary to understand and track all EMC mechanisms to meet EMC standards as most EMC problems are associated with a few dominant mechanisms.

By using high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.

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