Solving DDR4 timing problem with the help of SI analysis, real-life case study
One day we received an SOS call from Erik, who works at a company that develops communication systems.
Erik’s team was testing the hardware of their latest prototype, including an NXP QorIQ processor and DDR4 memory. They experienced some timing issues and were not able to get their hardware up and running. Our engineers investigated the board and found DDR4 timing issues using a Signal Integrity analysis(SI). We made a Board Support Package (BSP) with work-arounds. The result? Erik reacts relieved: ‘’In the end, we had the board up and running within a day.’’
‘’When we called, we had been trying to get our hardware up and running, without success’’
Erik’s team built their first design using DDR4 memory. They were careful to keep the DDR4 SDRAM implementation details close to reference designs. To avoid potential issues, they closely followed NXP application notes. PCB design was done with the help of external PCB consultants, who used Altium layout tools to keep crosstalk under control. To compensate for missing simulation tools, they chose a 12 layer PCB stack-up and paid close attention to line width, material parameters, line impedance, and termination resistors.
Before the call, Erik’s team had already done quite an extensive investigation. They had identified some design flaws. They had implemented work-arounds that allowed them to boot their boards and ran a few memory tests. The main issue at the time of calling was a failing clocks centering/adjustment test. We felt a little blindfolded, and didn’t know how to go proceed. We were seeking the help of someone who had done it before, and found Sintecs through the NXP website.”
‘’The nice thing about signal integrity analysis is that it does not just confirm that the problem is likely to occur, but also tells you where it comes from.’’
After signing the NDA we first and foremost focused on the signal integrity analysis for the DDR4. Based on signal integrity analysis and simulation results, we essentially concluded the same as Erik’s team had found in the prototype: ‘’The address bus and the clock would most likely not work.’’ The nice thing about signal integrity analysis is that it does not just confirm that the problem is likely to occur. It also tells you where it comes from, based on simulations. What we often notice when a design needs troubleshooting, is that the engineer has continued to use a way of working that always has been good practice – but no longer is. Such as in this case the conventional vias. With the help of the simulations, we could see that the use of standard vias led to reflection (ringback). Our advice to Erik was to use micro vias and buried vias in a subsequent design round, so that the reflections of the signals through the vias would be minimized. Redesigning the board, using a different PCB stack-up, was the only way to get rid of all problems.
‘’Sintecs gave the prototype boards more value than we expected when we called’’
Erik clarifies: ‘’Not only did Sintecs solve the DDR4 timing issues, they also helped with the Board Support Package, to quickly get the board up and running when we had issues with internal resource capacity.’’ Erik’s team had their first application up and running within a day after we delivered the BSP. “The small incremental deliveries helped us to develop the prototype step by step and helped us to meet a deadline.” “Sintecs gave the prototype boards more value than we expected initially. Ultimately we could get the boards up and running, and were able to test all the main parts of our prototype design. For that reason we’ll give them the assignment for the next prototype, earlier in the design. Sintecs will make the next PCB design with signal integrity and timing analysis to avoid issues before they arise.”
For reasons of discretion, we do not use our customer’s real name