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      Signal & Power Integrity analyzes; “Do everything possible to achieve 100% reliable hardware”

      SI & PI analyzes case study

      Shortly before the summer vacation, a lot of pressure came on a company in the Netherlands and Thomas called us for our expertise: “Signal & Power Integrity analyzes”. The company Thomas works for develops cameras for professional applications and ran into a problem with the mainboard of a new camera. “In the past, unstable hardware has been used, which greatly hampered software development,” explains Thomas. To prevent this issue with the new camera, we decided to have Signal and Power Integrity analyzes performed on the mainboard. The company who would initially do this turned out to be unable and Sintecs was therefore involved. 

      “The mainboard; heart of the new camera’’

      “The ITOR mainboard is seen as the heart of our new camera,” explains Thomas. The processing of the sensor to the image output is the task of this mainboard and in particular high image resolution and speed, 100 frames per second. A lot of data goes from the sensor board to the mainboard and on the latter board all data is converted, processed and brought back to a specific camera output. You can think of Camera Link, HD SDI and possibly USB3. The mainboard also does image processing; the memory and images are buffered in this memory. “Everything must be done in real time. The goal is to get a continuous output from the camera; with as little frame lag as possible, “says Thomas.


      ”It is definitely not pleasant if you constantly have to doubt whether your hardware works.”

      The importance of Signal & Power Integrity analyzes

      According to Thomas, Signal & Power Integrity analyzes are very important, especially when you work with high speed signals. “In the past it has happened that our hardware did not work properly. This has enormously slowed down the development of software at the time. It is definitely not pleasant if you constantly have to doubt whether your hardware works or not. If you work with high speed, for example a DDR 4 memory, you do not want to order the hardware without knowing it works. You just have to simulate that first, “says Thomas. “To be sure we would continue to work with reliable hardware, we asked Sintecs to perform these analyzes.” The question was whether our engineers could do these analyzes at all, and if so, whether they could start the next day already.


      “We received a lot of feedback in two weeks; a review has been done and simulation reports have been delivered and explained. Really good points and great value for money, that gives an amazing feeling!”

      The result

      The Sintecs engineers were able to start quickly. “Wouter started immediately with Signal Integrity analyzes on the DDR 4 memory and did Power Integrity simulations. This confirmed that we were not far wrong with our design and could continue with what we had made, “says Thomas. On the advice of our engineers, a number of schedule adjustments were made and the PCB design was optimized. “We received a lot of feedback in two weeks; a review has been done and simulation reports have been delivered and explained. Really good points and great value for money, that gives an amazing feeling! In addition, the analyzes and reports made it clear to us how everything worked. “

      The result? “In the end, our design was produced, the deadline was met and everything worked perfectly! Because the hardware is reliable and works for a long time, the software development will be the next focus, without any distraction of a potential hardware problem.”

      The organization where Thomas works for develops cameras for professional applications such as defense, site surveillance and the medical world. In connection with the application areas of these cameras we have agreed that the name of the company is not mentioned. The name of our conversation partner has also been changed.

      PCB-design for the NLR (Dutch Aerospace Center)

      Real-life PCB design case study

      The NLR was commissioned by the European Space Agency (ESA), to build a demonstrator for a new generation of on-board computers for satellites. The deadline was tight and the layout department of the NLR was too busy to handle this. Out of necessity the PCB design was outsourced to Sintecs.

      Application Engineer Filip Fontaine and R&D Engineer Bert-Johan Vollmuller explain on behalf of the Dutch Aerospace Center why they outsourced this assignment while they could do it themselves and they tell about how they experienced the collaboration with Sintecs.

      FFTC (Fast Fourier Transform Co-Processor)

      NLR is developing a new generation of on-board computers for satellites. This contains a fast FFT-chip, which makes a whole new series of satellite instruments and data processing of satellite images possible. A demonstrator board around an FFTC chip developed by ESA must demonstrate all the possibilities of the chip and show that the FFT is indeed fast enough for the next generations of measuring instruments.
      ‘’For a demonstrator, it is enough that you perform the key components in space-qualified conditions,’’ explains Vollmuller. ‘’The FFTC itself, the FPGA for controlling the FFTC, and the three SDRAMs are implemented in rad-hard technology. The rest (power conditioning, the Space Wire interfaces for command & control and Space Fibre for date input and output) can be done in commercial components.

      ‘’Why outsource if you can do it yourself?’’

      According to Vollmuller, NLR was under pressure of time because the board had to be ready by the end of 2018. “We developed the architecture and the scheme ourselves, and wrote the entire FPGA code. It is a complex board, with critical timing and very expensive components. A rad-hard FPGA costs ten thousand dollars. In principle, we can do the layout ourselves, but we did not have enough manpower in our layout department. We might not meet the deadline, resulting in a dissatisfied customer. Delay in planning is a much worse than the cost of the components. Therefore the complex layout had to be right in one go.”

      “We liked the interaction between designer and layouter, in order to arrive at a good solution”

      The NLR is used to do the layout in house. “This is a pleasant way of working, because there is a strong interaction between the engineer who makes the scheme and the layouter. We wondered how that would work if you outsource it and we were afraid that you give an order and see the first result 8 or 10 weeks later. Fortunately that was not the case,” says Vollmuller. Fontaine adds: “We had a lot of interaction during the layout phase, for example about the design decisions regarding the FPGA. In addition to the normal datasheet, there is a very thick book of application notes. Sintecs regularly contacted us to find out whether a design choice that we had made was intended. “Because something else is written in the application notes,” was the comment. In most cases we could say: ‘No, we really want it that way’, but a few times we thought ‘oh yes, that’s a good comment, we have to check that very carefully’. We would much rather have this than a layouter who does what we ask of him without thinking himself and that we would find out later that is not right yet. It is precisely this interaction between the designer and the layouter, in order to arrive at a good solution, that we liked. Sintecs actually did what we would normally do if we did the layout ourselves.


       “The hardware functioned immediately without problems”

      The result

      “Because there was a lot of interaction between us and the Sintecs layouter during the layout process, we had a lot of faith in the board. The result was that the hardware functioned immediately without any problems,” concluded Fontaine. “ESA was very enthusiastic that the project was completed before the end of 2018, and we at the NLR received compliments about that. Not only we are happy, our end customer is also happy. “


      Troubleshooting – A prototype that doesn’t work.

      Solving DDR4 timing problem with the help of SI analysis, real-life case study

      One day we received an SOS call from Erik, who works at a company that develops communication systems. 

      Erik’s team was testing the hardware of their latest prototype, including an NXP QorIQ processor and DDR4 memory. They experienced some timing issues and were not able to get their hardware up and running.  Our engineers investigated the board and found DDR4 timing issues using a Signal Integrity analysis(SI). We made a Board Support Package (BSP) with work-arounds. The result? Erik reacts relieved: ‘’In the end, we had the board up and running within a day.’’

      ‘’When we called, we had been trying to get our hardware up and running, without success’’

      Erik’s team built their first design using DDR4 memory. They were careful to keep the DDR4 SDRAM implementation details close to reference designs. To avoid potential issues, they closely followed NXP application notes. PCB design was done with the help of external PCB consultants, who used Altium layout tools to keep crosstalk under control. To compensate for missing simulation tools, they chose a 12 layer PCB stack-up and paid close attention to line width, material parameters, line impedance, and termination resistors.

      Before the call, Erik’s team had already done quite an extensive investigation. They had identified some design flaws. They had implemented work-arounds that allowed them to boot their boards and ran a few memory tests. The main issue at the time of calling was a failing clocks centering/adjustment test. We felt a little blindfolded, and didn’t know how to go proceed. We were seeking the help of someone who had done it before, and found Sintecs through the NXP website.” 

      ‘’The nice thing about signal integrity analysis is that it does not just confirm that the problem is likely to occur, but also tells you where it comes from.’’

      After signing the NDA we first and foremost focused on the signal integrity analysis for the DDR4. Based on signal integrity analysis and simulation results, we essentially concluded the same as Erik’s team had found in the prototype: ‘’The address bus and the clock would most likely not work.’’ The nice thing about signal integrity analysis is that it does not just confirm that the problem is likely to occur. It also tells you where it comes from, based on simulations. What we often notice when a design needs troubleshooting, is that the engineer has continued to use a way of working that always has been good practice – but no longer is. Such as in this case the conventional vias. With the help of the simulations, we could see that the use of standard vias led to reflection (ringback). Our advice to Erik was to use micro vias and buried vias in a subsequent design round, so that the reflections of the signals through the vias would be minimized. Redesigning the board, using a different PCB stack-up, was the only way to get rid of all problems.


      ‘’Sintecs gave the prototype boards more value than we expected when we called’’

      The result

      Erik clarifies: ‘’Not only did Sintecs solve the DDR4 timing issues, they also helped with the Board Support Package, to quickly get the board up and running when we had issues with internal resource capacity.’’ Erik’s team had their first application up and running within a day after we delivered the BSP. “The small incremental deliveries helped us to develop the prototype step by step and helped us to meet a deadline.” “Sintecs gave the prototype boards more value than we expected initially. Ultimately we could get the boards up and running, and were able to test all the main parts of our prototype design. For that reason we’ll give them the assignment for the next prototype, earlier in the design. Sintecs will make the next PCB design with signal integrity and timing analysis to avoid issues before they arise.”

      For reasons of discretion, we do not use our customer’s real name

      dReDBox – A design “right first time”

      The case study unveils some details of developing a powerful computing system

      At Sintecs, engineers from different teams, such as PCB layout and Signal / Power Integrity work closely together. We realize an optimal design by constantly monitoring from different expertise angles whether we are on the right track or not. Due to the continuous feedback that our engineers give each other, the design is adjusted where necessary. This method ensures that problems are solved, or even prevented.

      The project – dReDBox

       dReDBox is a Horizon 2020 EU project with the aim of more efficient use of data center resources, which saves space and energy. It is based on a new hardware concept in which a pool of disaggregated computing power, memory and acceleration resources are used instead of a fixed server configuration.


      The design

      dReDBox contains hardware building blocks, also referred to as “dBRICK”. Sixteen dBRICKs are stacked on the dTRAY, a connecting board with a high speed electrical-network that supports extreme low latency transactions from one dBRICK memory to another. dTRAY has three outgoing networks: an optical network, PCIe and ethernet.



      To make dReDBox easy to use for programmers, the platform supports Virtual Machine (VM) which configures resources on-the-fly to perfectly match user requirements.


      Challenges for Sintecs

      A disaggregate, high-performance computing platform is a complex ,high-end system. Our engineers have designed it from scratch, with a completely new architecture, a different physical distribution of processors and high speed memory, and high speed board-to-board interconnects. During the design phase of the dReDBox hardware we encountered three challenges.

      1. The speed of the DDR4-memory

      The dBRICKs rely on a stable DDR4 memory for fast, reliable operation. For a design like this, the timing margins are so tight that the exact physical configuration has a significant impact on the maximum memory speed. Timing analysis showed that it would be fundamentally impossible to use the memory at its maximum speed of 2400 MT/s if we kept to the PCB layout guidelines of the Zynq UltraScale + MPSoC. To get out of this deadlock, we asked Xilinx for more in-depth information. They collaborated and provided us with timing details that allowed us to optimize the PCB layout.

      Hardware verification on the first run of PCBs confirmed that we can indeed use the DDR4 memory at its maximum speed, in a broad temperature range, without timing violations nor EMI problems.

      2. Thermal analysis



      To avoid thermal issues, we performed thermal analysis and verification early in the design phase. We analyzed the individual dBRICKs and the complete dReDBox system, which dissipates an estimated 750 W. We identified hot spots, looked for zones of flow stagnation and identified overstressed components. The results of the thermal analysis served as an input for the mechanical and electrical design, reliability predictions and stress analyzes.

      Thermal modelling allowed us to optimize for airflow and temperature distribution, size and number of the fans. It gave insight in the impact of the configuration changes and failures of fans.

      3. Keep power dips and interference out

      To assure power integrity and absence of noise on the delivered power, we ran a signal and power integrity co-simulation. We determined the optimal decoupling, experimented with PCB stack-up, and examined many aspects of PCB technology such as used materials, dimensions, tracks and vias. We selected a solution which meets the power requirements yet avoids using exotic materials and processes that drive up costs.

      To mitigate the influence of fast switching high-speed interfaces on the dBRICKs and to avoid problems in its fifteen power rails, we adapted the layout of the planes and the decoupling capacitors so that they quickly distribute the large currents resulting from fast signal switching.

      No budget and no time for a redesign

      A PCB design iteration for a high-end system like this is around fifty thousand euros per round. The only way we could finish the dReDBox design in time and within the budget, is by making the design right the first time. And we managed that.



      How did we get a complex design like dReDBox up and running on the first round of PCBs? Whenever we made a design choice, we immediately analyzed it and acted on the analysis results, over and over as we were designing. We iterated, analyzed and optimized the hardware schematics. We could say that our way of working pays off.

      Customer case solving signal integrity issue

      Improving hardware performance by means of SI analysis

      We received a distress call from a company that creates RFID integrated systems. The company has tested multiple units and discovered that ~10% of the units contained an intermittent UBoot start up fail. Functional reviews and verification showed no obvious issues, errors or mistakes.

      After performing a review and analysis on signal integrity level we noticed that the boot loader IC (Flash) contained long traces with lots of vias and even a stub with a test pad attached to it. The simulation showed a remarkable result: at ‘fast corner case’ thresholds were violated and at ‘slow case’ it looked fine [Manufacturer default .ibs models]:

      The company already supplied the information that the units did boot correctly during ‘warm’ start, which corresponds to a slow corner case. Simulation results agreed. We took some systems with boot issues and warmed up the PCB. It worked like a charm. We cooled down the system and tried again. No signs of life.

      Most signals were routed on the top layer (stack up: 4 layers) which introduced a lot of crosstalk interference. The edge rates of this flash chip were between 100-300ps which is considered quite fast. The clock signal of this flash chip was not routed (2*w spacing and long traces) as recommended in the application note. The threshold violation during ‘cold’ start (‘fast case’) in combination with crosstalk (dV/dt of edge rate) problems created this intermittent error.  

      Without simulation, this root cause would probably have never been found.


      More information about signal integrity>>