As Hans Klos, CEO of Sintecs comments: “Having everything in one place eliminates the extra work caused by the lack of integration between design and testing tools”.
Baltic region is one of the fast growing IT clusters of the EU
Sintecs is opening an office in Lithuania to support growth in the Baltics region “This is an important step for our company. We have taken this step to expand on cooperation opportunities that we see in the Baltic market” said Hans Klos, founder and CEO. “We are starting with a new team of 6 experts in different disciplines and will be building a strong R&D team in Lithuania”.
Lithuania as one of the most fast-growing tech market of the EU
- Ranked 4th in the world in the Global Cybersecurity Index
- 1st place in EU by real GDP per capita growth 2000-2019
- 2nd place in EU for percent of 25-34 y.o. population with a higher education
- 3rd place globally by digital/technological skills availability
Check the press release of our partner Invest Lithuania for more information.
Contact details of the office:
Savickio st. 4, LT-01108
Common Signal Integrity Pitfalls
Enjoy the podcast with signal integrity expert Hans Klos CEO of Sintecs and learn about the Hyperlynx connector for Altium Designer, and get a really special subscription offer for Hyperlynx.
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About the importance of Signal Integrity even for a “low speed” design.
Applicable to: Hardware Engineer, PCB Layout Engineer, FPGA Engineer, PCB Architects and more.
Article author: Melvin Mengerink, Signal & Power Integrity Engineer at Sintecs.
Being a ‘hardware’ or layout engineer is a demanding position where a lot of variables and choices are constantly re-considered. These choices require in-depth knowledge of multiple disciplines, including high-speed signaling. Before we can design for high speed we must know what IS high speed. Even a low-frequency signal can have high-speed characteristics.
High speed is based on a reference level, otherwise high or low would have no meaning at all. With my current experience, high speed starts at > 1 GHz, but just before I started doing signal integrity analyses it was > 1 MHz. The difference between those moments is the amount of sheer knowledge I obtained in the last year. But, is it correct to qualify a signal as high speed just by the signal frequency, as seen in Figure 1?
In a perfect digital square waveform there are three main sections: The rising edge, the transition from logic ‘low’ to logic ‘high’, the constant voltages, GND: 0 V / VDD: 5 V and the falling edge, the transition from logic ‘high’ to logic ‘low’. I have taken a signal from 0 V to 5 V as an example. This, of course, depends on the signal created by the buffer drivers (e.g. FPGA).
The rise and fall times of IC components have seen major developments in the last couple of decades which still relates to Moore’s law of increasing transistor count per effective square mm. Smaller transistors make it possible to increase edge rates, thus enabling faster signaling speed. Unfortunately, this also applies to lower speed signals as the edge of modern IC’s remains incredibly fast.
The change between the constant voltages is called the fundamental frequency and can be low speed, e.g. 100MHz. Low speed, in this case, means that transmission line effects do not need immediate attention. But what about the rise and fall times?
If we look at Figure 2, we see that the AC component of the signal, by stitching the rise and fall times together, is much faster than the original signal. This is the part that behaves and propagates as a wave through the PCB.
The Fourier expansion of a digital ‘perfect’ square wave is composed of multiple sinusoids. Higher frequencies have a lower magnitude than lower frequencies and will be less ‘visible’ in the minimum and maximum regions of the waveform. The Fourier expansion, to determine the amplitude of the odd harmonics, is shown by equation 1 [Selby, 1973]:
Where n is the harmonic count, F is the frequency and t is the time.
If we would map this out in a graph it would look like Figure 3. We can see that the fundamental frequency (zeroth harmonic) is the average of the square wave (i.e. 0.5 x VDD). It declines rapidly with every odd harmonic. There are no even harmonics in a perfect square wave (duty cycle 50%).
Harmonics up to the 5th or 7th, sometimes even 9th, are usually considered in digital waveforms. You can see in figure 3 that the amplitude difference between the 7th and 9th is negligible. By not considering higher harmonics a bit of simulation accuracy is lost and reflections that are masked by this frequency will not be found. The lower amplitude of these harmonics will rarely cause any threshold violations. Including the harmonics into your design means that a proper signal transmission would require the consideration of 700 MHz, or 900 MHz signals, in lieu of the original 100 MHz signal frequency.
In order to make the call that a signal, or signal’s edge must comply to signal integrity regulations, one must first calculate the time delay of the signal, equation 2 [Hall and McCall, 2000]:
Where PD is the propagation delay, TD is the time delay, εr is the dielectric constant of the PCB or enclosing material and c is the speed of light. Epsilon r (dielectric constant) should be multiplied by the mu r (permeability), but including this variable makes the approximation a lot more difficult, so the permeability of air (=1) is chosen to simplify, meaning there are no magnetic materials in the vicinity.
The energy or EM waves, created by, e.g. a logic ‘low’ to a logic ‘high’ transition, is guided by the copper of the interconnect, meaning the ‘wave’ itself travels in the dielectric material. This material determines the maximum ‘speed’ (or propagation delay) of the signal. The trace geometry including the length of the interconnect determines the time delay. Therefore, the length is a critical parameter to sweep during the design.
If the time delay is bigger than or equal to 20% of the rise or fall time, signal integrity is relevant and the interconnect (trace) is considered a transmission line. This can and probably will result in inter-symbol interference (ISI) and reflections if not designed properly. If the propagating signal has already traveled forth (to the load) and back (to the source) before the next transition starts the interconnect is not considered a transmission line.
Do not underestimate the importance of signal integrity simulations and analysis. Even in a 133MHz signaling QSPI-bus, serious signal integrity issues have been found. In this article, I have shown that even low-frequency signals created by modern IC’s can have fast edges resulting in unintended transmission lines. Many of these issues are intermittent and very expensive to solve after the hardware is ordered.
A practical explanation of connection between EMC and Signal Integrity analysis
Many customers ask us if whether Signal & Power Integrity analysis can offer a solution for EMC problems. In order to answer this question, we asked Melvin Mengerink, Signal & Power Engineer at Sintecs, to explain wat EMC is and how it relates to SI & PI.
What is EMC?
ElectroMagnetic Compatibility is about a system being able to function correctly in an electromagnetic environment as well as quantifying its own radiation towards this same environment. EMC can be divided into two categories, EMR and EMI.
EMP and ESD are not included in this division.
- EMR: Electro Magnetic Radiation is the radiation that your system sends into the environment. This radiation can have a negative effect on nearby system that can cause system failure.
- EMI: Electro Magnetic Immunity is the susceptibility of your system in an electromagnetic environment created by nearby systems. These electromagnetic fields can also negatively affect the system causing system failures if threshold margins are slim or high-speed designs are used.
How does it relate to SI?
The creation of fringe fields is because a potential difference (E-field) is created. Due to this potential difference a current will start flowing, which will generate a magnetic field (B-field). If the signal integrity is of good quality the signal change will be limited to the edge transition. If reflections occur, due to impedance discontinuities, the signal can start to ring. This ringing will create a longer and more frequent change in signal potential, thus causing more EMR. Ringing or overshoot can also cause more crosstalk, inter-symbol interference or less threshold margin.
How does it relate to PI?
Power distribution networks (PDN’s) can also create EMR effects or be susceptible to EMI-problems. The name switching power supply already speaks for itself, but not only the switching behaviour has effect on the PDN power integrity. The PDN’s are used to create threshold levels for the digital logic circuitry. If the PDN is noisy or shows rail collapse and ground bounce issues the signals may be latched in unreliably. Variations and voltage fluctuations in a PDN can be the result of EMC (Transmitted) or EMI (Received) problems. To counter these effects proper decoupling and filtering must be used. PCB routing has a significant effect on EMC, EMI and power integrity response in general.
IBIS editor developed by Sintecs
IBIS Development Studio (IBISDS) is capable of viewing, editing and verifying IBIS models. You can view and edit the IBIS model in a graphical or in a text mode, whichever you need for your task. The model verification is done using the golden parser (IBIS version 5.0) and can be called directly from the IBISDS user interface.
The beauty of it is: You can use the IBIS viewer for free. As an extra, you can also use part of the editor functions for free in the viewer. For full editor functionality including the save functions, you need to buy a license.
The key features in the current release are:
- Model library; models can be easily loaded, edited, verified and saved to a central place.
- Template library; when you create new models from scratch each time, simply create a template for the model and store this in the template library.
- Using the model creation wizard it is easy to re-use the templates and quickly build new models.
- Easy editing; just drag and drop IBIS elements or move the nodes in the V/I curves. Syntax highlighting in text view, and more.
- EBD and PKG file support; IBIS models used in these files are detected and loaded for editing and verification.
- Error navigation for the golden parser.
- Easy change of large amount of pin model assignments.
- Advanced and easy to use IBIS model editor.
- FPGA support; makes it easy to create IBIS models based on pinning files.
Who will benefit the most of IBIS Development Studio?
- IBIS Model engineers
- Hardware and FPGA Designers
- Signal Integrity & Power Integrity engineers
To download the free version of IBIS DS please fill out the form below.