Where PD is the propagation delay, TD is the time delay, εr is the dielectric constant of the PCB or enclosing material and c is the speed of light. Epsilon r (dielectric constant) should be multiplied by the mu r (permeability), but including this variable makes the approximation a lot more difficult, so the permeability of air (=1) is chosen to simplify, meaning there are no magnetic materials in the vicinity.

The energy or EM waves, created by, e.g. a logic ‘low’ to a logic ‘high’ transition, is guided by the copper of the interconnect, meaning the ‘wave’ itself travels in the dielectric material. This material determines the maximum ‘speed’ (or propagation delay) of the signal. The trace geometry including the length of the interconnect determines the time delay. Therefore, the length is a critical parameter to sweep during the design.

If the time delay is bigger than or equal to 20% of the rise or fall time, signal integrity is relevant and the interconnect (trace) is considered a transmission line. This can and probably will result in inter-symbol interference (ISI) and reflections if not designed properly. If the propagating signal has already traveled forth (to the load) and back (to the source) before the next transition starts the interconnect is not considered a transmission line.

**Final word:**

Do not underestimate the importance of signal integrity simulations and analysis. Even in a 133MHz signaling QSPI-bus, serious signal integrity issues have been found. In this article, I have shown that even low-frequency signals created by modern IC’s can have fast edges resulting in unintended transmission lines. Many of these issues are intermittent and very expensive to solve after the hardware is ordered.

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