Shortly before the summer vacation, a lot of pressure came on a company in the Netherlands and Thomas called us for our expertise: “Signal & Power Integrity analyzes”. The company Thomas works for develops cameras for professional applications and ran into a problem with the mainboard of a new camera. “In the past, unstable hardware has been used, which greatly hampered software development,” explains Thomas. To prevent this issue with the new camera, we decided to have Signal and Power Integrity analyzes performed on the mainboard. The company who would initially do this turned out to be unable and Sintecs was therefore involved. 

“The mainboard; heart of the new camera’’

“The ITOR mainboard is seen as the heart of our new camera,” explains Thomas. The processing of the sensor to the image output is the task of this mainboard and in particular high image resolution and speed, 100 frames per second. A lot of data goes from the sensor board to the mainboard and on the latter board all data is converted, processed and brought back to a specific camera output. You can think of Camera Link, HD SDI and possibly USB3. The mainboard also does image processing; the memory and images are buffered in this memory. “Everything must be done in real time. The goal is to get a continuous output from the camera; with as little frame lag as possible, “says Thomas.

”It is definitely not pleasant if you constantly have to doubt whether your hardware works.”

The importance of Signal & Power Integrity analyzes

According to Thomas, Signal & Power Integrity analyzes are very important, especially when you work with high speed signals. “In the past it has happened that our hardware did not work properly. This has enormously slowed down the development of software at the time. It is definitely not pleasant if you constantly have to doubt whether your hardware works or not. If you work with high speed, for example a DDR 4 memory, you do not want to order the hardware without knowing it works. You just have to simulate that first, “says Thomas. “To be sure we would continue to work with reliable hardware, we asked Sintecs to perform these analyzes.” The question was whether our engineers could do these analyzes at all, and if so, whether they could start the next day already.

“We received a lot of feedback in two weeks; a review has been done and simulation reports have been delivered and explained. Really good points and great value for money, that gives an amazing feeling!”

The result

The Sintecs engineers were able to start quickly. “Wouter started immediately with Signal Integrity analyzes on the DDR 4 memory and did Power Integrity simulations. This confirmed that we were not far wrong with our design and could continue with what we had made, “says Thomas. On the advice of our engineers, a number of schedule adjustments were made and the PCB design was optimized. “We received a lot of feedback in two weeks; a review has been done and simulation reports have been delivered and explained. Really good points and great value for money, that gives an amazing feeling! In addition, the analyzes and reports made it clear to us how everything worked. “

The result? “In the end, our design was produced, the deadline was met and everything worked perfectly! Because the hardware is reliable and works for a long time, the software development will be the next focus, without any distraction of a potential hardware problem.”

We received a distress call from a company that creates RFID integrated systems. The company has tested multiple units and discovered that ~10% of the units contained an intermittent UBoot start up fail. Functional reviews and verification showed no obvious issues, errors or mistakes.

After performing a review and analysis on signal integrity level we noticed that the boot loader IC (Flash) contained long traces with lots of vias and even a stub with a test pad attached to it. The simulation showed a remarkable result: at ‘fast corner case’ thresholds were violated and at ‘slow case’ it looked fine [Manufacturer default .ibs models]:

The company already supplied the information that the units did boot correctly during ‘warm’ start, which corresponds to a slow corner case. Simulation results agreed. We took some systems with boot issues and warmed up the PCB. It worked like a charm. We cooled down the system and tried again. No signs of life.

Most signals were routed on the top layer (stack up: 4 layers) which introduced a lot of crosstalk interference. The edge rates of this flash chip were between 100-300ps which is considered quite fast. The clock signal of this flash chip was not routed (2*w spacing and long traces) as recommended in the application note. The threshold violation during ‘cold’ start (‘fast case’) in combination with crosstalk (dV/dt of edge rate) problems created this intermittent error.  

Without simulation, this root cause would probably have never been found.

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