In high-end designs, high-speed behaviour often affects more than 80% of the signals on the board.
Transmission line behaviour is complex and simulating it is essential to get an understanding of signal behaviour. Manufacturing tolerances of various components must be considered in the simulations, for the combinations specific for the design.
Investigating signal integrity in any step in the design process gives insight into how everything onboard influences the outcome. This way you can take out signal integrity issues before the PCB goes in production
Modern-day multifunctional devices support aggressive, multiple timing variations in their designs. All timings must be perfectly aligned to get the design up and running fast, without any intermittent failures in the resulting PCBs.
For high-speed DDR memories, perfect timing and compensation for any latency between clock lines and address lines are key to guarantee fast, stable and reliable memory operation at the maximum speed supported. Differences in trace lengths, the use of vias and cross-talk all influence timing for high-speed designs.
To design out any timing disturbances and avoid intermittent failures in the product, timing analysis and verification early in the design phase is key.