Improving hardware performance by means of SI analysis
We received a distress call from a company that creates RFID integrated systems. The company has tested multiple units and discovered that ~10% of the units contained an intermittent UBoot start up fail. Functional reviews and verification showed no obvious issues, errors or mistakes.
After performing a review and analysis on signal integrity level we noticed that the boot loader IC (Flash) contained long traces with lots of vias and even a stub with a test pad attached to it. The simulation showed a remarkable result: at ‘fast corner case’ thresholds were violated and at ‘slow case’ it looked fine [Manufacturer default .ibs models]:
The company already supplied the information that the units did boot correctly during ‘warm’ start, which corresponds to a slow corner case. Simulation results agreed. We took some systems with boot issues and warmed up the PCB. It worked like a charm. We cooled down the system and tried again. No signs of life.
Most signals were routed on the top layer (stack up: 4 layers) which introduced a lot of crosstalk interference. The edge rates of this flash chip were between 100-300ps which is considered quite fast. The clock signal of this flash chip was not routed (2*w spacing and long traces) as recommended in the application note. The threshold violation during ‘cold’ start (‘fast case’) in combination with crosstalk (dV/dt of edge rate) problems created this intermittent error.
Without simulation, this root cause would probably have never been found.