+31 74 2555 713 info@sintecs.nl


+31 74 2555 713

Signal Integrity


What is signal integrity?

Signals on a PCB travel from one electric component to another. When the signal that arrives at a component is not of good quality, the board can become instable or dysfunctional, especially at higher speeds.


What can go wrong?

If signal integrity is compromised, the signal will be distorted. Effects like overshoot, ringing, switching noise, skew, IR-drop, etc. may occur. This will cause functional problems like timing errors, threshold issues, crosstalk, EMI emission, and local hot spots.


What is the cause?

The signal quality does not only depend on the design or PCB routing (interconnect length, characteristic impedance, via usage, delay, decoupling, power distribution network design, etc), but also on IC die technology, IC package parasitics, wave propagation in diëlectricum layers, etc.


When does it occur?

The principles behind signal integrity apply to any electronic design. Signal integrity issues however are more likely to cause problems when: data transfer speeds are higher, rise and fall times are faster (die technology), core voltages are lower and thus currents are higher, and interconnect distances are larger (PCB complexity). So beware if you are using a CPU or FPGA in combination with DDR3, DDR4, PCIe, USB 3.0, SerDes, or Gigabit Ethernet.


What can you do about it?

It is not always enough to design carefully, and layout according to design rules. Signal integrity analysis, based on full-wave solver algorithms, will show how signals behave precisely. Next, the layout is modified to fix signal integrity issues, thus increasing the robustness of the design.


What are the benefits of that approach?

Pinpointing signal integrity issues in a prototype costs a lot of lab effort, and fixing the issues is not always possible. Performing signal integrity analysis as part of the design saves a lot of trial-and-error, reduces the number of prototype iterations, creates more stable electronics, and decreases time to market.